OldDogBlog post 12
The previous blogs got me to a point where I’m confident I can do this project with the self-imposed constraints of using a small FPGA in a BGA package with a 2-layer PCB as the goal. Time for the schematic.
When I started college I was pursuing a degree in architecture. Long story short, I realized that good architects were also, to some degree, good artists. It wasn’t long before I realized I had very little artistic ability and I subsequently changed majors to electrical engineering. Interestingly, engineering offered me opportunities to be…artistic. It turns out that schematics and PCB layouts are works of art. In fact, in the old days, we called a PCB layout and “artwork.”
Schematics can also tell a story. A good schematic makes it easy to follow flow and understand function. It should be clean with a lot of white space and copious notes describing the design. One way to make a schematic cleaner is to have as few net crossovers as possible. I like inputs on the left and outputs on the right of a symbol too, if possible.
The key component of any schematic is the symbols for the individual components. In a previous blog post I decided to use a company called MacroFab in Houston, TX to build and stuff the boards. They have a number of “house parts” available that are offered at discount prices and are guaranteed to be in stock. They also have KiCad symbols and footprints available so I downloaded the libraries. It is a good starting point and the component footprints have already been proven by MacroFab to be correct.
I then had to create my own symbols for the FPGA, USB/Serial port, oscillator, regulator, and several 0.1” headers. Overall there weren’t many symbols to create so the process went quickly. Symbols for FPGAs can be problematic because FPGA I/O pins can be inputs or outputs depending on how you use them. You might also have to swap FPGA pins during board layout in order to get things to fit and route better. Worse, the next time you use the part on a different project, the entire I/O pin out might be completely different.
For every symbol but the FPGA, it was easy enough to keep inputs on the left and outputs on the right. For the FPGA, I opted this time to not worry so much about inputs on the left etc. Instead I grouped all the I/O I expected to use on the upper part of the symbol with pins on the left and right sides. Pins I knew I wouldn’t use were put on the lower left and right sides of the symbol. Power pins were along the top and ground pins along the bottom. Configuration pins were grouped together along the bottom left side.
Knowing that I planned on using this FPGA for future projects, I first drew a generic symbol called 10M08_UBGA169_a. The “a” at the end indicates it is a baseline symbol that will allow me to make different symbols and simply change to “b”, “c” etc. I can then attach the same footprint to these different symbols. The generic symbol is shown in Figure 1. The symbol I used on the ezPixel schematic is 10M08_UBGA169_b.
Figure 1: Generic FPGA symbol
To accommodate my desire to minimize the number of wires crossing over each other on the drawing, I opted to connect all the FPGA I/O with hanging nets. Each net has a name indicating which FPGA pin it connects to. Not perfect, but the end result is workable as the number of signal nets is small.
There isn’t much to the schematic and it fits easily on a single page. The finished design is shown in Figure 2. NOTE: All of the source files to make ezPixel will be posted on GitHub and made open source after a crowd funding campaign in January, 2018.
Figure 2: ezPixel schematic.
I took a best guess on how the FPGA signals would connect to the translator chips and also picked some pins to connect to the USB/Serial chip. In all likelihood some pin swaps will happen during layout so best guesses are good enough.
Once the schematic is complete I ran design rule checks in KiCad to verify that nothing obvious was wrong with the design. This is a crucial step – before moving to layout the schematic should pass all design rule checks error free.
The final schematic includes mounting holes, fiducials, and has the power and ground planes established. With the design rules checks running error free, I can finally move to PCB layout.