“Plane” and simple.

OldDogBlog Post 11.

In this post I’ll talk a bit about how I did the escape routing for the MAX10 FPGA in the 169 UBGA package on just two circuit board layers. Four circuit board layers is more traditional for a BGA package with this many pins, but I wanted to avoid the additional recurring expense of a 4-layer board versus a 2-layer board.

This is where the color coded drawing started to come in handy. Back in post #9 I showed a drawing I made indicating the locations of power, ground, and configuration pins on the BGA package. Figure 1 re-creates that image with just the power and ground pins highlighted. I addressed power and ground first, since they are fundamental to the chip operation. On most of the circuit boards I’ve designed I use power and ground planes to distribute those signals instead of discrete traces. All of the chip components on this board require power and ground, as do decoupling capacitors and some connector pins. Planes make it fairly simple to connect to powers and ground and make the routing job simpler and faster. There are other electrical benefits to using as well but that is for another post.

For ezPixel I decided on using a ground plane on the component or “top” side of the board and two power planes on the “bottom” side of the board – one power plane for +5V and another for +3.3V. Using nothing more than a pencil it was quick work to try a variety of different ways to connect to power and ground with just two layers. It should be noted that the picture shows two different voltage pins on the FPGA – +3.3V and VCCA. VCCA is a separate voltage related to use of the on-chip analog-to-digital converter in the FPGA. ezPixel will not be using the ADC and therefore VCCA can connect to the same plane as the rest of the +3.3V pins.

Figure 1: Power and Ground pins.

I tackled +5V power routing first since none of it goes to the BGA but it does impact where the BGA would sit on the board. In a previous post I hinted that the level translator chips would most likely surround the FPGA. That became clearer now. The only components that needed to connect to +5V were one side of each level translator, the USB serial chip, and the USB connector. The +5V plane could form a “U” shape around 3 sides of the board and all the rest of the bottom would be the +3.3V plane as shown in Figure 2.

Figure 2: Candidate Voltage Planes.

Next up were the ground pins. It was clear that the four ground pins on the corners of the chip would be easy to route directly to the ground plane surrounding the chip. The remaining connections, however, were buried farther inside the grid and would probably need to be routed on the bottom side of the board. A good rule of thumb is to try and keep power and ground signal traces as short as possible and connect directly to planes as much as is practicable. How was that going to happen when the ground plane was on the top of the board and so many ground pins were inside the grid? It would be so much simpler if there was a ground plane on the bottom of the board….

Duh!

In a brick-to-the-forehead moment of clarity I realized I could put a ground plane on the bottom too.

Figure 3 shows a chunk of ground plane on the bottom of the board, surrounded by +3.3V plane. This ground plane chunk would probably be oddly shaped and would need copious connections to the top side ground plane so that any return currents in this segment of the plane could flow freely to the main ground plane. This chunk of bottom side ground plane would allow me to connect BGA inner row ground pins to a ground plane without needing to snake long traces around lots of pins. Also, having a section of ground plane on the back of the board created the possibility of adding decoupling capacitors on the bottom of the board close the power pins which is also a good thing. Lastly, by not having to snake ground pin traces out from under the BGA, it left more room for snaking I/O and config pins out.

Figure 3: Bottom-Side Ground Plane Segment.

The exact size and shape of each plane, and the ground plane segment would be determined in layout.

I still had to worry about breaking out configuration and JTAG pins, but at this point I could ball park estimate that I’d have access to ~50 I/O pins. This was more than I absolutely needed for ezPixel but many years of experience – a polite way of saying “epic fails” – has taught me that having extra I/O pins available is always worth doing. I decided to use every possible I/O that I could break out from the BGA.

Using simple pencil and paper allowed me to very quickly feel confident that I could break out enough pins for ezPixel plus some spares and keep it all on two layers. But, to do a layout, one needs a schematic done first…

Woof!

Tom Burke

MakerLogic.com

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