OrCad, KiCad, Eagle, Lizard, Spock

OldDogBlog post 9.

In this post I’ll discuss the free design tools I used for schematic capture and PCB layout. Like all things tech related, these CAD tools have their fan boys and detractors. I’ve used all of them at one time or another, plus some others that are no longer in existence.

In my day job my circuit schematics frequently get turned over to another person who specializes in doing the PCB layout. However, in my own non-day job projects I get to do my own PCB layouts. For home use I ruled out tools I would have to pay for. I wanted to explore whether or not free tools could produce results as good as I was used to with paid tools. So, no OrCad and no Altium.

How about Eagle?

I started using Eagle several years ago as it was free-ish but for non-commercial use only. I couldn’t continue to use it for free if I wanted to sell ezPixels. Eagle also restricts the board size and layer count with the free version of the tools. I decided that if I was going to build up a library of trusted component footprints, I should use a tool that won’t restrict board size and layer count. So, add Eagle to the list of tools that I won’t be using.

I ultimately switched to KiCad as it is 100% free and doesn’t have the restrictions that Eagle imposes. Some of the restrictions aren’t hugely important for this project, but who knows what future projects I’ll pursue?

In a previous post I described choosing an Intel MAX10 FPGA in a BGA package. This provided a good unit cost and would force me into doing a board layout with a BGA device – something I haven’t done personally before.

It is quite common to use four or more board layers with BGA parts to fully breakout all the BGA pins and more easily route to good power and ground planes. However, adding more board layers increases the cost of the bare PCB, which wasn’t desirable. So, in an effort to add even more challenges to the project, I aimed for a 2-layer board.

After deciding on the FPGA part and package, I downloaded a host of additional documentation from Intel. This was no easy feat as the MAX10 support web page constantly jumps around with what it displays. Very annoying! The extra information includes:

  • Pin-out information for 10M02SA, 10M04SA, 10M08SA, 10M16SA. All of these devices can fit on the same 169-in UBGA footprint. I downloaded them in spreadsheet format as a personal preference. They can also be had in .pdf and .txt formats.
  • 169-pin Ultra FineLine Ball-Grid Array (UBGA) package drawings. This is needed to make a proper footprint for the circuit board layout.
  • MAX10 Device Errata. Always check this before finalizing a design! Some feature you are counting on may not work as planned…
  • MAX10 FPGA Design Guidelines 2017.05.03
  • Board Design Guidelines at this website: https://www.altera.com/support/support-resources/support-centers/board-design-guidelines.html

For devices this small a handy visualization tool I use is to create a ball grid array in LibreOffice Impress. I then identify each pin as power, ground, configuration, I/O and no-connect and color-coded them on the drawing – Figure 1.

Figure 1: Top View of 169 Pin BGA.

I printed out some color copies and worked with a pencil to quickly sketch out ideas for power and ground connections first – nothing is faster than a pencil for quickly iterating ideas. Power and ground are crucial because without either the chip simply doesn’t work.

I then looked at configuration/JTAG pins because you can’t use the part if you can’t configure it. What was left after that were the easily accessible GPIO pins. I expected the usable I/O to primarily be the first two rows of balls all around the perimeter of the chip. However, sketching out connections to power, ground, and configuration pins indicated that I might not be able to use all the available GPIOs. I would find that out during board layout.

The GPIO pin locations inform me of potential placement of the level translators around the FPGA. I need 32 GPIO pins to connect to the translators. I’ll explore trace width and spacing in the next post.


Tom Burke


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