OldDogBlog post 10.
In this post I’ll discuss the decisions that are made while getting ready for component placement and board layout. The most important component on ezPixel is the FPGA and it is also the largest component with the most signal traces to contend with. My goal is to keep the board physically small as it will cost less to manufacture. Bare circuit boards are predominantly priced by the square inch area and number of layers. The board will have at least 32 outputs to control strings, plus extra signals for SPI, UART and some spare signals. To make the board easy to connect to, I’ll plan on having a single row of pins on each edge of the board.
This suggests that the FPGA should be centrally located with signals fanning out towards the board edges. The challenge is connecting to enough pins inside the ball grid array on a two layer board. Adding more board layers would make layout process simpler but would increase the cost of the bare boards. The first step is determine how wide the signal traces must be to fit between the balls and what the minimum distance is between a trace and anything else. These are known as the “board geometry” or the “trace and space” values.
Figure 1 shows the dimensions of the BGA package for the ezPixel FPGA shown in Intel document 04R-00470-2.0. This information is needed to determine the trace and space values. The important number we need is the “pitch” of the balls, i.e. the spacing from the center of one ball to the center of adjacent balls. This is shown in Figure 1 as the “e” dimension which is 0.8mm for the UBGA169 package.
Figure 1: BGA Package Dimensions.
The other information we need is the size of the pad on the PCB that the BGA balls will sit on. This will not be the same size as the ball itself – it is usually a bit smaller in diameter. This is shown in Intel AN-114, Table 3. The row in the table for BGA Pad Pitch = 0.80mm UBGA (wirebond) shows the Solder Ball Diameter as 0.50mm and the Recommended NSMD Pad Size = 0.34mm. AN-114 is an excellent source for learning about PCB layout terminology and to see examples of suggested signal trace breakout methods. Figure 2 shows the pad spacing dimensions for the UBGA169 we are using.
Figure 2: Via and Routing Space for UBGA169.
Figure 2 lets us determine what the trace and space values will be to fit between two balls. As an OldDog, I’ll be discussing values using mils, short for milli-inch and not millimeters. One mil = 1/1000 of an inch. As can be seen, the dimension between the edges of two adjacent balls is 18.11 mils. Theoretically this would allow a trace width of 6 mils with a 6 mil space on each side of the trace. 6+6+6 = 18 mils.
Most board fab houses these days can handle 6/6 trace/space geometry. However, being a conservative OldDog, I think it is prudent to leave more space between the balls and the trace. Using a 5 mil trace would allow almost 7 mils between the trace and the ball, assuming the trace is run down the center between two balls. On the flip-side, smaller geometry might cost more – many board houses will charge more for geometry below 6/6.
With a little digging I found a company in Texas – MacroFab – that will do 5 mil trace/space at no extra cost. Plus, they specialize in small volume prototype PCB assembly which is important as I was using a BGA device and didn’t plan on trying hand assembly. MacroFab also hosts a weekly engineering podcast that you may find interesting. https://macrofab.com/blog/podcast/
5 mil geometry allows one trace between the balls of the BGA. This immediately limits the pins I will be able to connect to. The outer row and first inner row are readily achievable, but I would have to be careful with connections to inner row configuration, power and ground pins. Referring back to the color-coded pin drawing in OldDogBlog post 9, you can see that some of the configuration and JTAG pins are as many as 6 rows deep into the ball grid array.
In the next post I’ll look at how to tackle the goal of breaking out the BGA and staying on two layers.